A. Technical Field
The present invention relates generally to digital circuit design, and more particularly, to the design of volatile circuits that contain volatile data states that may be lost without the continued application of applied power. An example of such a volatile circuits are digital memory circuits capable of retaining the data state of each memory cell during power-down periods in which the primary power source for the memory circuit is uncoupled from the memory circuit or, otherwise, interrupted or rendered inactive to the memory circuit. A particular example of such a memory circuit is a random access memory (RAM) circuit.
B. Background of the Invention
An ongoing trend to reduce the size of the components in integrated memory circuits is leading to geometries that enable the operation of memory circuits using a lowered power level of about 1.8 volts. Power at this level is typically provided from a conventional unregulated external power source of about 3.0 volt by an internal low drop out (hereinafter “LDO”) power supply regulator. Nonetheless, when such low voltage devices are inactivated or turned off, such as for backup or standby, the leakage currents exhibited are substantially large compared to those in devices configured using earlier versions of CMOS technology that typically operate from an unregulated external power source of about 3.0 volts with lower leakage current.
In modern CMOS processes, adequately low standby currents cannot be achieved simply by making all circuit nodes in such a circuit design static because of excessive leakage currents in such smaller geometry devices when placed in an “off” or inactive state. Previous solutions to this problem have concentrated on employing analog circuit techniques to reduce such leakage current. Examples of these techniques are the employment, for example, of a reverse substrate bias and the interposition of much less leaky high voltage transistors in each leakage path, such as employing thicker gate oxide, deeper device junctions and the employment of larger dimension devices or transistor elements. These solutions are complex and do not guarantee the desired results.
What is needed is a way to provide for memory circuit backup of their volatile memory states of the newer lower voltage operating CMOS circuits using an approach that provides for lower leakage during periods of circuit power inactivation or turn-off. The approach here utilizes digital circuit state retention in the absence of circuit power.